This invention relates to a programmable logic device having embedded random access memory. More particularly, this invention relates to such a programmable logic device in which the embedded random access memory is a dual-port memory that can be configured, using resources of the programmable logic device, as a single-port memory.
Programmable logic devices are well known. Such devices typically include a plurality of programmable logic cells or elements arranged on a single integrated circuit chip. A programmable interconnection structure allows a user, typically with the assistance of a dedicated software tool, to configure the device as any type of logic, within the capabilities of the device, that may be required. In order to facilitate the various configurations, the device typically is arranged as a two-dimensional array of logic cells or elements, and typically is provided with interconnection conductors that run vertically and horizontally within the array, although various ring configurations of conductors are also known. Depending on the design of the particular device, the conductors may run the length or breadth of the device, or may span only a portion of the device; many devices have combinations of conductors of various types. Whatever their type, conductors usually run in parallel groups or groups. The interconnection conductors are complemented by programmable interconnection resources that allow various conductors to be connected together and to particular inputs or outputs of the various logic cells or elements.
In early programmable logic devices, the programmable interconnection resources included fully populated matrices where interconnection conductors crossed, allowing any conductor in one group of interconnection conductors to be connected to any conductor in the intersecting group of interconnection conductors. As programmable logic devices became larger in size, it became impractical to provide such fully populated interconnections, because of the physical space they required on the integrated circuit chip. In current devices, it is common for most programmable interconnection resources to be less than fully populated. For example, in many cases, programmable interconnection resources are provided in the form of multiplexers. Using statistical techniques, based on likely user requirements, sufficient programmable interconnection resources are provided so that substantially any signal routing that a user might want to implement will be possible using some combination of interconnection conductors and programmable interconnection resources.
It has become common to provide on-board random access memory (RAM) as part of programmable logic devices. This particularly true in, but is not limited to, programmable logic devices whose logic elements are based on look-up tables implemented in static random access memory (SRAM). When RAM is provided on a programmable logic device, it may be configurable as logic elements, or it may be used to satisfy other memory requirements of the end user""s logic configuration.
It is known to provide single-port RAMxe2x80x94i.e., RAM having a single port through which both read and write operations are conductedxe2x80x94on a programmable logic device. It is also known to combine two blocks of single-port RAM on a programmable logic device to emulate dual-port RAMxe2x80x94i.e., RAM having separate ports for reading and writing thereby allowing simultaneous read and write operations. One way of emulating dual-port RAM is to write all data to be stored in the RAM into both single-port RAM blocks, but to read from only one of the RAM blocks. This requires directing both addressing signals and data to be stored to both RAM blocks. An alternative approach is to use a single single-port RAM block to emulate a dual-port RAM by time-multiplexing read and write operations. However, this approach reduces by half the effective speed of the RAM. Using either approach, the various signals and data must be routed to the proper ports via the programmable interconnect structure of the programmable logic device.
It would be desirable to be able to provide a programmable logic device having embedded random access memory that can function equally well in either single-port or dual-port operation.
It is an object of the invention to provide a programmable logic device having embedded random access memory that can function equally well in either single-port or dual-port operation.
In accordance with the present invention, there is provided a programmable logic device having a plurality of logic resources, a plurality of groups of interconnection conductors for interconnecting the logic resources, and a plurality of programmable interconnection resources for connecting conductors in the groups of interconnection conductors to one another and to the plurality of logic resources, with the programmable interconnection resources being less than fully populated. The programmable logic device further includes at least one random access memory having a read port and a write port, a first programmable interconnection resource in the plurality of programmable interconnection resources for connecting port conductors in the read port to a selected one of the plurality of groups of interconnection conductors, and a second programmable interconnection resource in the plurality of programmable interconnection resources for connecting port conductors in the write port to the selected one of the plurality of groups of interconnection conductors. The first and second programmable interconnection resources are populated to allow connection of an individual conductor in the selected one of the plurality of groups of interconnection conductors to corresponding port conductors in both the read port and the write port.
The present invention achieves faster speeds for dual-port RAM in a programmable logic device by providing a true dual-port RAM. This eliminates the need to time-multiplex read and write operations, and therefore effectively doubles the speed available in previous programmable logic devices in which a single-port RAM was used with time-multiplexing of read and write operations on the same port. Alternatively, this eliminates the waste of using two RAMS to emulate a single RAM as described above.
When the dual-port RAM provided in accordance with the present invention is used in a programmable logic device of the type described above, each port must be connected to the interconnect structure of the programmable logic device so that signals can be sent to and received from the RAM. This presents potential difficulties, because, although in the present invention dual-port RAM is provided in a programmable logic device in the place of single-port RAM as previously known in programmable logic devices, there may be instances when the user""s desired configuration requires the availability of single-port RAM. As described above, in many types of programmable logic devices the programmable interconnection resources are not fully populated. Thus, the port conductors in the read and write ports of a dual-port RAM provided in accordance with the present invention might not be connectable to the same group of conductors, and even if they are they might not be connectable to the same conductors within that group of conductors.
Therefore, in accordance with the present invention, both ports of the dual-port RAM are connected to programmable interconnection resources that connect them to the same group of conductors. Moreover, the programmable interconnection resources are populated in such a way that each pair of corresponding port conductors in the two ports can be connected the same individual conductor in the associated group of conductors.
Accordingly, if a user configuration of the programmable logic device requires the availability of single-port RAM, the programmable interconnection resources are configured so that corresponding read port conductors and write port conductors are connected to the same interconnection conductors of the programmable logic device. Then, in operation, the remainder of the circuit sends either a read address signal or a write address signal, as the case may be, to what it sees as a single destination just as it would with a standard single-port RAM. In fact, identical signals arrive at the two separate ports, but only the signals at one port are acted upon, in accordance with a read/write selection or enable signal that the circuit sends to enable either the read operation or the write operation of what it xe2x80x9cthinksxe2x80x9d is a single port. Thus, to the remainder of the programmable logic device, the dual-port RAM xe2x80x9clooksxe2x80x9d like a single-port RAM, using all of the same signals as a conventional single-port RAM.
According to a first preferred embodiment, the programmable interconnection resources for the read port and the write port are, at least with respect to the read and write ports, identically populatedxe2x80x94i.e., the programmable interconnection resources are provided such that each port conductor in one of the ports can be connected to all of the same interconnection conductors to which the corresponding conductor in the other of the ports can be connected. It is not necessary according to this embodiment of the invention, however, for the programmable interconnection resources to be identically populated with respect to other interconnection conductors not used by either port, although such completely identical population of the programmable interconnection resources is within the present invention.
In a second preferred embodiment according to the invention, the programmable interconnection resources for the read port and the write port are not identically populated even with respect to the ports themselves. In this embodiment, each port conductor in one of the ports can be connected to at least one interconnection conductor to which the corresponding port conductor in the other of the ports can be connected, but corresponding port conductors might not share all of the same interconnection conductors.
Both of the aforementioned embodiments allow the dual-port RAM provided in accordance with the present invention to function as a single-port RAM by providing at least one combination of conductor assignments that allows identical address and control signals to reach both ports. The first embodiment allows more than one such possible set of conductor assignments, increasing flexibility in configuring the dual-port RAM of the device as single-port RAM, at possible expense of flexibility in configuring other functions of the overall programmable logic device. The second embodiment provides the reverse, allowing a smaller number, or perhaps only one, possible configuration of the dual-port RAM as a single-port RAM, but increasing flexibility in programming other functions of the overall programmable logic device.